// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:12 UTC 2022
//////////////////////////////////////////////////////////////////////////////
//
//  pcs_raw_mem_decode.v
//
//  Raw PCS memory decoder
//
//  Original Author: Dom Spagnuolo
//  Current Owner:   Dom Spagnuolo
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: spagnuol $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_mem_decode.v $
//    $DateTime: 2015/10/26 08:06:03 $
//    $Revision: #3 $
//
//////////////////////////////////////////////////////////////////////////////

// Mantis 6909 - include appropriate macro files
`include "dwc_e12mp_phy_x4_ns_cr_macros.v"
`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_mem_decode #(parameter CR_TYPE = `DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_ROM0) (
// CREG parallel interface
input  wire                       cr_clk,
input  wire                       cr_rst,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_addr,

output  wire [31:0]               cr_cmn0_b0_sel,
output  wire [31:0]               cr_cmn0_b1_sel,
output  wire [31:0]               cr_cmn0_b2_sel,
output  wire [31:0]               cr_cmn0_b3_sel,
output  wire [31:0]               cr_cmn0_b4_sel,
output  wire [31:0]               cr_cmn0_b5_sel,
output  wire [31:0]               cr_cmn0_b6_sel,
output  wire [31:0]               cr_cmn0_b7_sel,

output  wire [31:0]               cr_cmn1_b0_sel,
output  wire [31:0]               cr_cmn1_b1_sel,
output  wire [31:0]               cr_cmn1_b2_sel,
output  wire [31:0]               cr_cmn1_b3_sel,
output  wire [31:0]               cr_cmn1_b4_sel,
output  wire [31:0]               cr_cmn1_b5_sel,
output  wire [31:0]               cr_cmn1_b6_sel,
output  wire [31:0]               cr_cmn1_b7_sel,

output  wire [31:0]               cr_cmn2_b0_sel,
output  wire [31:0]               cr_cmn2_b1_sel,
output  wire [31:0]               cr_cmn2_b2_sel,
output  wire [31:0]               cr_cmn2_b3_sel,
output  wire [31:0]               cr_cmn2_b4_sel,
output  wire [31:0]               cr_cmn2_b5_sel,
output  wire [31:0]               cr_cmn2_b6_sel,
output  wire [31:0]               cr_cmn2_b7_sel,

output  wire [31:0]               cr_cmn3_b0_sel,
output  wire [31:0]               cr_cmn3_b1_sel,
output  wire [31:0]               cr_cmn3_b2_sel,
output  wire [31:0]               cr_cmn3_b3_sel,
output  wire [31:0]               cr_cmn3_b4_sel,
output  wire [31:0]               cr_cmn3_b5_sel,
output  wire [31:0]               cr_cmn3_b6_sel,
output  wire [31:0]               cr_cmn3_b7_sel,

output  wire [31:0]               cr_cmn4_b0_sel,
output  wire [31:0]               cr_cmn4_b1_sel,
output  wire [31:0]               cr_cmn4_b2_sel,
output  wire [31:0]               cr_cmn4_b3_sel,
output  wire [31:0]               cr_cmn4_b4_sel,
output  wire [31:0]               cr_cmn4_b5_sel,
output  wire [31:0]               cr_cmn4_b6_sel,
output  wire [31:0]               cr_cmn4_b7_sel,

output  wire [31:0]               cr_cmn5_b0_sel,
output  wire [31:0]               cr_cmn5_b1_sel,
output  wire [31:0]               cr_cmn5_b2_sel,
output  wire [31:0]               cr_cmn5_b3_sel,
output  wire [31:0]               cr_cmn5_b4_sel,
output  wire [31:0]               cr_cmn5_b5_sel,
output  wire [31:0]               cr_cmn5_b6_sel,
output  wire [31:0]               cr_cmn5_b7_sel,

output  wire [31:0]               cr_cmn6_b0_sel,
output  wire [31:0]               cr_cmn6_b1_sel,
output  wire [31:0]               cr_cmn6_b2_sel,
output  wire [31:0]               cr_cmn6_b3_sel,
output  wire [31:0]               cr_cmn6_b4_sel,
output  wire [31:0]               cr_cmn6_b5_sel,
output  wire [31:0]               cr_cmn6_b6_sel,
output  wire [31:0]               cr_cmn6_b7_sel,

output  wire [31:0]               cr_cmn7_b0_sel,
output  wire [31:0]               cr_cmn7_b1_sel,
output  wire [31:0]               cr_cmn7_b2_sel,
output  wire [31:0]               cr_cmn7_b3_sel,
output  wire [31:0]               cr_cmn7_b4_sel,
output  wire [31:0]               cr_cmn7_b5_sel,
output  wire [31:0]               cr_cmn7_b6_sel,
output  wire [31:0]               cr_cmn7_b7_sel,

output  wire [31:0]               cr_cmn8_b0_sel,
output  wire [31:0]               cr_cmn8_b1_sel,
output  wire [31:0]               cr_cmn8_b2_sel,
output  wire [31:0]               cr_cmn8_b3_sel,
output  wire [31:0]               cr_cmn8_b4_sel,
output  wire [31:0]               cr_cmn8_b5_sel,
output  wire [31:0]               cr_cmn8_b6_sel,
output  wire [31:0]               cr_cmn8_b7_sel,

output  wire [31:0]               cr_cmn9_b0_sel,
output  wire [31:0]               cr_cmn9_b1_sel,
output  wire [31:0]               cr_cmn9_b2_sel,
output  wire [31:0]               cr_cmn9_b3_sel,
output  wire [31:0]               cr_cmn9_b4_sel,
output  wire [31:0]               cr_cmn9_b5_sel,
output  wire [31:0]               cr_cmn9_b6_sel,
output  wire [31:0]               cr_cmn9_b7_sel,

output  wire [31:0]               cr_cmn10_b0_sel,
output  wire [31:0]               cr_cmn10_b1_sel,
output  wire [31:0]               cr_cmn10_b2_sel,
output  wire [31:0]               cr_cmn10_b3_sel,
output  wire [31:0]               cr_cmn10_b4_sel,
output  wire [31:0]               cr_cmn10_b5_sel,
output  wire [31:0]               cr_cmn10_b6_sel,
output  wire [31:0]               cr_cmn10_b7_sel,

output  wire [31:0]               cr_cmn11_b0_sel,
output  wire [31:0]               cr_cmn11_b1_sel,
output  wire [31:0]               cr_cmn11_b2_sel,
output  wire [31:0]               cr_cmn11_b3_sel,
output  wire [31:0]               cr_cmn11_b4_sel,
output  wire [31:0]               cr_cmn11_b5_sel,
output  wire [31:0]               cr_cmn11_b6_sel,
output  wire [31:0]               cr_cmn11_b7_sel,

output  wire [31:0]               cr_cmn12_b0_sel,
output  wire [31:0]               cr_cmn12_b1_sel,
output  wire [31:0]               cr_cmn12_b2_sel,
output  wire [31:0]               cr_cmn12_b3_sel,
output  wire [31:0]               cr_cmn12_b4_sel,
output  wire [31:0]               cr_cmn12_b5_sel,
output  wire [31:0]               cr_cmn12_b6_sel,
output  wire [31:0]               cr_cmn12_b7_sel,

output  wire [31:0]               cr_cmn13_b0_sel,
output  wire [31:0]               cr_cmn13_b1_sel,
output  wire [31:0]               cr_cmn13_b2_sel,
output  wire [31:0]               cr_cmn13_b3_sel,
output  wire [31:0]               cr_cmn13_b4_sel,
output  wire [31:0]               cr_cmn13_b5_sel,
output  wire [31:0]               cr_cmn13_b6_sel,
output  wire [31:0]               cr_cmn13_b7_sel,

output  wire [31:0]               cr_cmn14_b0_sel,
output  wire [31:0]               cr_cmn14_b1_sel,
output  wire [31:0]               cr_cmn14_b2_sel,
output  wire [31:0]               cr_cmn14_b3_sel,
output  wire [31:0]               cr_cmn14_b4_sel,
output  wire [31:0]               cr_cmn14_b5_sel,
output  wire [31:0]               cr_cmn14_b6_sel,
output  wire [31:0]               cr_cmn14_b7_sel,

output  wire [31:0]               cr_cmn15_b0_sel,
output  wire [31:0]               cr_cmn15_b1_sel,
output  wire [31:0]               cr_cmn15_b2_sel,
output  wire [31:0]               cr_cmn15_b3_sel,
output  wire [31:0]               cr_cmn15_b4_sel,
output  wire [31:0]               cr_cmn15_b5_sel,
output  wire [31:0]               cr_cmn15_b6_sel,
output  wire [31:0]               cr_cmn15_b7_sel

);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE0) )
cmn0_creg (
  .cr_cmn_b0_sel         (cr_cmn0_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn0_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn0_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn0_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn0_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn0_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn0_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn0_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE1) )
cmn1_creg (
  .cr_cmn_b0_sel         (cr_cmn1_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn1_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn1_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn1_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn1_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn1_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn1_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn1_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE2) )
cmn2_creg (
  .cr_cmn_b0_sel         (cr_cmn2_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn2_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn2_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn2_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn2_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn2_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn2_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn2_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE3) )
cmn3_creg (
  .cr_cmn_b0_sel         (cr_cmn3_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn3_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn3_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn3_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn3_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn3_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn3_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn3_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE4) )
cmn4_creg (
  .cr_cmn_b0_sel         (cr_cmn4_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn4_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn4_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn4_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn4_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn4_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn4_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn4_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE5) )
cmn5_creg (
  .cr_cmn_b0_sel         (cr_cmn5_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn5_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn5_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn5_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn5_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn5_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn5_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn5_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE6) )
cmn6_creg (
  .cr_cmn_b0_sel         (cr_cmn6_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn6_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn6_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn6_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn6_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn6_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn6_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn6_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE7) )
cmn7_creg (
  .cr_cmn_b0_sel         (cr_cmn7_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn7_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn7_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn7_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn7_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn7_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn7_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn7_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE8) )
cmn8_creg (
  .cr_cmn_b0_sel         (cr_cmn8_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn8_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn8_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn8_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn8_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn8_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn8_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn8_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE9) )
cmn9_creg (
  .cr_cmn_b0_sel         (cr_cmn9_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn9_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn9_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn9_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn9_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn9_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn9_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn9_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE10) )
cmn10_creg (
  .cr_cmn_b0_sel         (cr_cmn10_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn10_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn10_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn10_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn10_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn10_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn10_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn10_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE11) )
cmn11_creg (
  .cr_cmn_b0_sel         (cr_cmn11_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn11_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn11_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn11_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn11_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn11_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn11_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn11_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE12) )
cmn12_creg (
  .cr_cmn_b0_sel         (cr_cmn12_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn12_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn12_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn12_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn12_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn12_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn12_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn12_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE13) )
cmn13_creg (
  .cr_cmn_b0_sel         (cr_cmn13_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn13_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn13_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn13_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn13_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn13_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn13_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn13_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE14) )
cmn14_creg (
  .cr_cmn_b0_sel         (cr_cmn14_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn14_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn14_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn14_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn14_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn14_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn14_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn14_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

dwc_e12mp_phy_x4_ns_pcs_raw_mem_creg #(.CR_TYPE(CR_TYPE),
                   .CR_LANE(`DWC_E12MP_X4NS_CR_MEM_LANE15) )
cmn15_creg (
  .cr_cmn_b0_sel         (cr_cmn15_b0_sel),
  .cr_cmn_b1_sel         (cr_cmn15_b1_sel),
  .cr_cmn_b2_sel         (cr_cmn15_b2_sel),
  .cr_cmn_b3_sel         (cr_cmn15_b3_sel),
  .cr_cmn_b4_sel         (cr_cmn15_b4_sel),
  .cr_cmn_b5_sel         (cr_cmn15_b5_sel),
  .cr_cmn_b6_sel         (cr_cmn15_b6_sel),
  .cr_cmn_b7_sel         (cr_cmn15_b7_sel),
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);


endmodule

